FPGA Design Engineer
Our client is a technology-oriented company developing advanced space-based remote sensing solutions for environmental monitoring and resource management. The organization develops high-resolution Earth observation capabilities, combining sophisticated sensing technologies, onboard processing, and satellite systems to deliver recurrent and actionable planetary data.
Its activities rely on close collaboration between multidisciplinary engineering teams working across electronics, embedded systems, FPGA development, image processing, and software. The company combines a strong engineering foundation with an agile, fast-paced development environment, offering professionals the opportunity to contribute to technically demanding systems with real-world environmental and operational impact.
Mission
The FPGA Design Engineer will be responsible for architecting and developing next-generation image acquisition and processing payloads, managing the complete high-speed data path from physical FPGA interfaces and raw sensor acquisition through hardware processing, AI acceleration, DMA transfers, and memory. The role will ensure robust, synchronized, low-latency operation while driving FPGA design, integration, verification, and optimization across advanced Xilinx/AMD platforms.
Responsibilities
FPGA Architecture and RTL Development
- Design, develop, and optimize modular VHDL architectures for Xilinx 7-Series, UltraScale+, and Versal Adaptive SoCs.
- Optimize RTL implementations through efficient utilization of DSP48 slices, Block RAM, UltraRAM, and other FPGA resources.
- Translate payload and mission requirements into reliable, scalable FPGA architectures.
High-Speed I/O and Data Path
- Implement and debug high-speed transceivers and interfaces, including GTH/GTY-based connectivity for MIPI CSI-2, PCIe Gen3/4, and 10G/25G Ethernet.
- Architect low-latency data paths using AXI4-Stream, AXI SmartConnect, VDMA, DataMover, and Scatter-Gather DMA architectures.
- Configure and optimize DDR4/LPDDR4 memory subsystems for high-bandwidth, multi-stream image and video buffering.
AI Integration and Timing Optimization
- Deploy and optimize neural networks through Vitis AI, integrating DPU acceleration cores into FPGA-based processing architectures.
- Define complex XDC constraints and manage multiple clock domains using MMCMs and PLLs.
- Drive timing closure and performance optimization on high-utilization FPGA designs.
Verification and Engineering Practices
- Develop advanced simulation and self-checking verification environments using technologies such as UVVM, OSVVM, UVM, XSIM, ModelSim/Questa, and Xilinx Verification IP.
- Perform hardware-in-the-loop verification and debugging using Vivado ILA, Vitis Analyzer, and relevant high-speed signal analysis techniques.
- Contribute to engineering documentation, internal procedures, technical specifications, knowledge sharing, and continuous improvement initiatives.
Required Qualifications
- BSc or MSc in Electronics, Telecommunications Engineering, or a closely related discipline.
- Deep expertise in VHDL and Xilinx-specific RTL design and resource optimization.
- Advanced proficiency with Vivado Design Suite, Vitis Unified Software Platform, and PetaLinux.
- Extensive experience with Xilinx IP Integrator and the AXI4 protocol family, including Memory Mapped, Stream, and Lite.
- Practical experience with high-speed hardware, including SerDes calibration, eye-diagram analysis, and high-speed PCB constraints.
- Proven experience implementing DMA and Scatter-Gather DMA architectures for high-bandwidth sensor data.
- Strong verification experience using advanced simulation environments and self-checking testbenches.
- Experience with XSIM or third-party simulation environments such as ModelSim/Questa and Xilinx Verification IP.
- Proficiency in Tcl for Vivado automation and Python for engineering data analysis.
- Fluent professional English.
Preferred Experience
- Experience with Versal AI Engines and the Programmable Network on Chip.
- Familiarity with Vitis HLS and C/C++-to-RTL synthesis for accelerated IP development.
- Experience with FPGA-based AI acceleration and neural-network deployment workflows.
- Familiarity with high-reliability or space-oriented FPGA design, including Single Event Upset mitigation and radiation-aware design principles.